公开(公告)号：US10593596B2

公开(公告)日：2020-03-17

申请号：US15959319

申请日：2018-04-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongwoo Han ,  Kwang-Yong Yang ,  Jinwook Lee ,  Kyungyub Jeon ,  Haegeon Jung ,  Dohyoung Kim

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L21/306

Abstract: A method of fabricating a semiconductor device includes forming first and second active patterns on first and second regions, respectively, of a substrate, forming first and second gate structures on the first and second active patterns, respectively, forming a coating layer to cover the first and second gate structures and the first and second active patterns, and forming a first recess region in the first active pattern between the first gate structures and a second recess region in the second active pattern between the second gate structures.

公开(公告)号：US09984931B2

公开(公告)日：2018-05-29

申请号：US15260952

申请日：2016-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongwoo Han ,  Kwang-Yong Yang ,  Jinwook Lee ,  Kyungyub Jeon ,  Haegeon Jung ,  Dohyoung Kim

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L21/306

CPC classification number: H01L21/823431 ,  H01L21/30604 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/6656 ,  H01L29/66795

Abstract: A method of fabricating a semiconductor device includes forming first and second active patterns on first and second regions, respectively, of a substrate, forming first and second gate structures on the first and second active patterns, respectively, forming a coating layer to cover the first and second gate structures and the first and second active patterns, and forming a first recess region in the first active pattern between the first gate structures and a second recess region in the second active pattern between the second gate structures.