公开(公告)号：US20240063113A1

公开(公告)日：2024-02-22

申请号：US18192031

申请日：2023-03-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghun CHUN ,  HOYOUNG CHOI ,  Haeli PARK ,  JEEHOON HAN

IPC: H01L23/522 ,  H10B43/27 ,  H10B41/27 ,  H10B80/00 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H10B43/27 ,  H10B41/27 ,  H10B80/00 ,  H01L21/76804 ,  H01L21/76829 ,  H10B41/10

Abstract: A semiconductor device including: a first gate stack including first insulating patterns and first conductive patterns; a second gate stack on the first gate stack, the second gate stack including second insulating patterns and second conductive patterns; a memory channel structure penetrating the first and second gate stacks; a penetration contact penetrating the first and second gate stacks; and a barrier pattern on opposite sides of the penetration contact, the first insulating patterns include a first connection insulating pattern, which is an uppermost one of the first insulating patterns, the second insulating patterns include a second connection insulating pattern which is in contact with a top surface of the first connection insulating pattern, a bottom surface of the barrier pattern is in contact with the top surface of the first connection insulating pattern, and a top surface of the barrier pattern is in contact with the second connection insulating pattern.