公开(公告)号：US12200106B2

公开(公告)日：2025-01-14

申请号：US17698639

申请日：2022-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae Hun Jang ,  Ji Youp Kim ,  Han Byeul Na ,  Young Suk Ra ,  Man Keun Seo ,  Hong Rak Son ,  Se Jin Lim

IPC: H04L9/06 ,  G06F3/06 ,  G06F21/60 ,  G06F21/72

Abstract: A memory device includes an input unit configured to receive a plain text and output plain blocks and CTS plain block, a multi-core unit including a plurality of encryption/decryption cores configured to encrypt each of the plain blocks provided from the input unit and output cipher blocks in accordance with control of an encryption/decryption core control unit, a CTS core unit including a CTS core configured to encrypt the CTS plain block provided from the input unit into a CTS cipher block, and an output unit configured to receive the cipher blocks and the CTS cipher block and output a cipher text. The CTS plain block is generated through a CTS calculation based on the plain text.