公开(公告)号：US20240155842A1

公开(公告)日：2024-05-09

申请号：US18510736

申请日：2023-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyo Joon RYU ,  Seo-Goo KANG ,  Hee Suk KIM ,  Jong Seon AHN ,  Kohji KANAMORI ,  Jee Hoon HAN

IPC: H10B43/27 ,  H01L23/522 ,  H10B41/27

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H10B41/27

Abstract: A semiconductor memory device includes a lower stacked structure with lower metal lines on a substrate, an upper stacked structure with an upper metal line on the lower stacked structure, a vertical structure penetrating the upper and lower stacked structures and including a channel layer, a first cutting line through the upper and lower stacked structures, an upper supporter in a recess on the first cutting line, a second cutting line through the upper and lower stacked structures and spaced apart from the first cutting line, a sub-cutting line through the upper stacked structure while at least partially overlapping the vertical structure in the vertical direction, the sub-cutting line being between the first and second cutting lines, top surfaces of the upper supporter and sub-cutting line being coplanar, and a first interlayer insulating layer surrounding a sidewall of each of the upper supporter and the sub-cutting line.