公开(公告)号：US20200380360A1

公开(公告)日：2020-12-03

申请号：US16890045

申请日：2020-06-02

Applicant: Samsung Electronics Co., Ltd. ,  UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Hyeongseok YU ,  Hyeonuk SIM ,  Jongeun LEE

IPC: G06N3/08 ,  G06N3/04

Abstract: A processor-implemented method includes determining a first quantization value by performing log quantization on a parameter from one of input activation values and weight values in a layer of a neural network, comparing a threshold value with an error between a first dequantization value obtained by dequantization of the first quantization value and the parameter, determining a second quantization value by performing log quantization on the error in response to the error being greater than the threshold value as a result of the comparing; and quantizing the parameter to a value in which the first quantization value and the second quantization value are grouped.

公开(公告)号：US20210174177A1

公开(公告)日：2021-06-10

申请号：US16893560

申请日：2020-06-05

Applicant: Samsung Electronics Co., Ltd. ,  UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Hyeongseok YU ,  Hyeonuk SIM ,  Jongeun LEE

IPC: G06N3/063 ,  G06N3/04

Abstract: A neural network device includes: an on-chip buffer memory that stores an input feature map of a first layer of a neural network, a computational circuit that receives the input feature map of the first layer through a single port of the on-chip buffer memory and performs a neural network operation on the input feature map of the first layer to output an output feature map of the first layer corresponding to the input feature map of the first layer, and a controller that transmits the output feature map of the first layer to the on-chip buffer memory through the single port to store the output feature map of the first layer and the input feature map of the first layer together in the on-chip buffer memory.

公开(公告)号：US20230085442A1

公开(公告)日：2023-03-16

申请号：US17987079

申请日：2022-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Hyeongseok YU ,  Hyeonuk SIM ,  Jongeun LEE

IPC: G06N3/08 ,  G06N3/04

Abstract: A processor-implemented method includes determining a first quantization value by performing log quantization on a parameter from one of input activation values and weight values in a layer of a neural network, comparing a threshold value with an error between a first dequantization value obtained by dequantization of the first quantization value and the parameter, determining a second quantization value by performing log quantization on the error in response to the error being greater than the threshold value as a result of the comparing; and quantizing the parameter to a value in which the first quantization value and the second quantization value are grouped.

公开(公告)号：US20240169190A1

公开(公告)日：2024-05-23

申请号：US18314512

申请日：2023-05-09

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Hyeonuk SIM ,  Sangyun OH ,  Jongeun LEE

IPC: G06N3/0495 ,  G06F5/01

CPC classification number: G06N3/0495 ,  G06F5/01

Abstract: An electronic device includes: a shifter configured to perform a shift operation based on a codebook supporting a plurality of quantization levels preset for data bits of a data set; and a decoder configured to control the shifter by setting quantization scales of the data bits differently for preset groups, wherein the shifter is configured to quantize and output the data bits by control of the decoder.

公开(公告)号：US20240143274A1

公开(公告)日：2024-05-02

申请号：US18311509

申请日：2023-05-03

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Hyeonuk SIM ,  Jongeun LEE ,  Azat AZAMAT

IPC: G06F5/01 ,  G06F7/499

CPC classification number: G06F5/01 ,  G06F7/49947

Abstract: A neural network operation apparatus and method are disclosed. A neural network operation apparatus includes a receiver that receives data for a neural network operation, and a processor that performs a scaling operation by multiplying the data by a constant, performs a rounding operation by truncating bits forming a result of the scaling operation, performs a scaling back operation based on a result of the rounding operation, and generates a neural network operation result by accumulating results of the scaling back operation.

公开(公告)号：US20240411516A1

公开(公告)日：2024-12-12

申请号：US18734138

申请日：2024-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Penghui WEI ,  Gang SUN ,  Jiao WU ,  Hyeonuk SIM

IPC: G06F7/523

Abstract: A precision allocation method and device based on a neural network processor are provided. The precision allocation method includes allocating a weight of a neural network to a multiplier column of a neural network processor, determining a lower tolerance for the multiplier column, and selecting a first data type for the multiplier column from a plurality of data types based on the lower tolerance, wherein each of the plurality of data types corresponds to a different precision level, and performing, by the neural network processor, a multiplication operation based on the weight and the first data type.

公开(公告)号：US20240184533A1

公开(公告)日：2024-06-06

申请号：US18326563

申请日：2023-05-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeonuk SIM

IPC: G06F7/74 ,  G06F5/01

CPC classification number: G06F7/74 ,  G06F5/01

Abstract: A computing apparatus include a processing circuitry configured to detect a weight depth field, related to a range of a weight value of a plurality of weight values, within the weight value, and detect an activation depth field, related to a range of an activation value of a plurality of activation values, within the activation value; identify a first operand in the weight value, and identify a second operand in the activation value; and generate an output value having a resultant depth field determined based on the weight depth field and the activation depth field, by performing an operation based on the identified first and second operands.

公开(公告)号：US20240046082A1

公开(公告)日：2024-02-08

申请号：US18489209

申请日：2023-10-18

Applicant: Samsung Electronics Co., Ltd. ,  UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Hyeongseok YU ,  Hyeonuk SIM ,  Jongeun LEE

IPC: G06N3/063 ,  G06N3/04

CPC classification number: G06N3/063 ,  G06N3/04

Abstract: A neural network device including an on-chip buffer memory that stores an input feature map of a first layer of a neural network, a computational circuit that receives the input feature map of the first layer through a single port of the on-chip buffer memory and performs a neural network operation on the input feature map of the first layer to output an output feature map of the first layer corresponding to the input feature map of the first layer, and a controller that transmits the output feature map of the first layer to the on-chip buffer memory through the single port to store the output feature map of the first layer and the input feature map of the first layer together in the on-chip buffer memory.

公开(公告)号：US20220284262A1

公开(公告)日：2022-09-08

申请号：US17368470

申请日：2021-07-06

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Sehwan LEE ,  Hyeonuk SIM ,  Jongeun LEE

IPC: G06N3/04

Abstract: A neural network operation apparatus and method implementing quantization is disclosed. The neural network operation method may include receiving a weight of a neural network, a candidate set of quantization points, and a bitwidth for representing the weight, extracting a subset of quantization points from the candidate set of quantization points based on the bitwidth, calculating a quantization loss based on the weight of the neural network and the subset of quantization points, and generating a target subset of quantization points based on the quantization loss.