公开(公告)号：US20220171913A1

公开(公告)日：2022-06-02

申请号：US17380200

申请日：2021-07-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sooyong Lee ,  Jeeyong Lee ,  Seunghune Yang ,  Hyeyoung Ji

IPC: G06F30/398 ,  G06N20/00

Abstract: With respect to each layout pattern of a plurality of layout patterns included in a layout for semiconductor processes, where the layout includes schematic information to form process patterns of a semiconductor device, vertical features indicating an effect of a lower structure on the process patterns are determined, and the lower structure indicates a structure that is formed in the semiconductor device before the process patterns are formed. A machine learning module is trained based on a training layout and the vertical features of the training layout. A design layout with schematic information to form target process patterns is corrected based on the trained machine learning module, the design layout and the vertical features of the design layout. Reliability and integration of the layout for the semiconductor processes may be increased by correcting the layout based on the vertical features and the horizontal features.

公开(公告)号：US12086526B2

公开(公告)日：2024-09-10

申请号：US17380200

申请日：2021-07-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sooyong Lee ,  Jeeyong Lee ,  Seunghune Yang ,  Hyeyoung Ji

IPC: G06F30/398 ,  G06N20/00

CPC classification number: G06F30/398 ,  G06N20/00

Abstract: With respect to each layout pattern of a plurality of layout patterns included in a layout for semiconductor processes, where the layout includes schematic information to form process patterns of a semiconductor device, vertical features indicating an effect of a lower structure on the process patterns are determined, and the lower structure indicates a structure that is formed in the semiconductor device before the process patterns are formed. A machine learning module is trained based on a training layout and the vertical features of the training layout. A design layout with schematic information to form target process patterns is corrected based on the trained machine learning module, the design layout and the vertical features of the design layout. Reliability and integration of the layout for the semiconductor processes may be increased by correcting the layout based on the vertical features and the horizontal features.