公开(公告)号：US20240429192A1

公开(公告)日：2024-12-26

申请号：US18401625

申请日：2023-12-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHAJEA JO ,  Jaejun Lee ,  Hyiyeong Jang

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/10 ,  H01L25/18 ,  H10B80/00

Abstract: A semiconductor package includes a lower semiconductor chip including a first circuit layer, an upper semiconductor chip disposed on the lower semiconductor chip and including a second circuit layer, and an interconnection layer disposed between the lower semiconductor chip and the upper semiconductor chip, the interconnection layer including a plurality of pads, including at least a first pad offset from the lower semiconductor chip or the upper semiconductor chip, and a wiring portion horizontally extended and connecting the first pad of the plurality of pads to a second pad of the plurality of pads disposed between the lower semiconductor chip and the upper semiconductor chip, wherein the wiring portion of the interconnection layer electrically connects the first circuit layer to the second circuit layer.