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公开(公告)号：US11861280B2
公开(公告)日：2024-01-02
申请号：US17692883
申请日：2022-03-11
发明人： In Huh , Jeong-hoon Ko , Hyo-jin Choi , Seung-ju Kim , Chang-wook Jeong , Joon-wan Chai , Kwang-il Park , Youn-sik Park , Hyun-sun Park , Young-min Oh , Jun-haeng Lee , Tae-ho Lee
摘要： A method of reinforcement learning of a neural network device for generating a verification vector for verifying a circuit design comprising a circuit block includes inputting a test vector to the circuit block, generating one or more rewards based on a coverage corresponding to the test vector, the coverage being determined based on a state transition of the circuit block based on the test vector, and applying the one or more rewards to a reinforcement learning.
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公开(公告)号：US20220198111A1
公开(公告)日：2022-06-23
申请号：US17692883
申请日：2022-03-11
发明人： In Huh , Jeong-hoon Ko , Hyo-jin Choi , Seung-ju Kim , Chang-wook Jeong , Joon-wan Chai , Kwang-il Park , Youn-sik Park , Hyun-sun Park , Young-min Oh , Jun-haeng Lee , Tae-ho Lee
摘要： A method of reinforcement learning of a neural network device for generating a verification vector for verifying a circuit design comprising a circuit block includes inputting a test vector to the circuit block, generating one or more rewards based on a coverage corresponding to the test vector, the coverage being determined based on a state transition of the circuit block based on the test vector, and applying the one or more rewards to a reinforcement learning.
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公开(公告)号：US11281832B2
公开(公告)日：2022-03-22
申请号：US16788924
申请日：2020-02-12
发明人： In Huh , Jeong-hoon Ko , Hyo-jin Choi , Seung-ju Kim , Chang-wook Jeong , Joon-wan Chai , Kwang-il Park , Youn-sik Park , Hyun-sun Park , Young-min Oh , Jun-haeng Lee , Tae-ho Lee
摘要： A device for verifying a circuit design including a first circuit block and a second circuit block includes a verification vector generator and a design verifier. The verification vector generator determines a first verification vector by performing reinforcement learning through neural network computation based on a coverage corresponding to a first test vector, the coverage being determined based on a state transition of the first circuit block generated by inputting the first test vector to the first circuit block. The design verifier performs design verification for the first circuit block by using the first verification vector.
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