公开(公告)号：US20210391433A1

公开(公告)日：2021-12-16

申请号：US17313638

申请日：2021-05-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNGMIN KIM ,  JUHUN PARK ,  DEOKHAN BAE ,  MYUNGYOON UM ,  YURI LEE ,  INYEAL LEE ,  YOONYOUNG JUNG ,  SOOYEON HONG

IPC: H01L29/417 ,  H01L27/092

Abstract: A semiconductor device includes a first active (e.g., PMOSFET) region and an adjacent second active (e.g., NMOSFET) region on a substrate, a device isolation layer on the substrate and defining a first active pattern on the first active region and a second active pattern on the second active region, a gate electrode crossing the first and second active patterns, a first source/drain pattern and a second source/drain pattern adjacent to a side of the gate electrode, an interlayer insulating layer on the gate electrode, a first active contact penetrating the interlayer insulating layer to connect the first source/drain pattern and a second active contact penetrating the interlayer insulating layer to connect the second source/drain pattern and a buffer layer provided in an upper region of the interlayer insulating layer and interposed between the first active contact and the second active contact, wherein the buffer layer includes a material having etch selectivity with respect to the interlayer insulating layer.