公开(公告)号：US11532336B2

公开(公告)日：2022-12-20

申请号：US17340423

申请日：2021-06-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyojin Choi ,  Jaewon Ko ,  Hyeongtae Kim ,  Younsik Park ,  Hyeonsik Son

IPC: G11C7/00 ,  G11C7/10 ,  G11C11/408 ,  G11C29/00

Abstract: A memory device including: a memory cell array including a plurality of memory cell rows; an address buffer configured to store addresses of target rows of the plurality of memory cell rows, wherein the addresses of the target rows have been repeatedly accessed; a minimum access output circuit configured to select, when there are a plurality of rows having a same minimum access count among the target rows, any one of the plurality of rows having the same minimum access count as a minimum access row based on a selection command value, and to output an index value of the minimum access row; and a control circuit configured to output a command instructing replacement of an address corresponding to the index value of the minimum access row with an address of an access row and storage of the address of the access row in the address buffer.