公开(公告)号：US20190296047A1

公开(公告)日：2019-09-26

申请号：US16441163

申请日：2019-06-14

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Sung-il CHANG ,  Jun-Hee LIM ,  Yong-Seok KIM ,  Tae-Young KIM ,  Jae-Sung SIM ,  Su-Jin AHN ,  Ji-Yeong HWANG

IPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L29/78 ,  H01L29/66 ,  H01L27/11578 ,  H01L21/265 ,  H01L27/11556

摘要： In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.