公开(公告)号：US11064603B2

公开(公告)日：2021-07-13

申请号：US16270874

申请日：2019-02-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-woon Park ,  Jin-an Lee

IPC: H05K1/02 ,  H01L25/18 ,  H01L23/538 ,  H01L23/66 ,  H05K1/18

Abstract: Provided is an electronic apparatus capable of improving time margin. The electronic apparatus includes: a base substrate including a substrate base including a plurality of layers and a plurality of wiring layers between the layers; a controller chip and at least one memory semiconductor chip mounted on the base substrate; a signal line disposed in one of the wiring layers and connecting the controller chip to the at least one memory semiconductor chip; and a pair of open stubs disposed in another wiring layer, connected to both ends of the signal line, and extending to face each other with a gap.

公开(公告)号：US20190357351A1

公开(公告)日：2019-11-21

申请号：US16270874

申请日：2019-02-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-woon PARK ,  Jin-an Lee

IPC: H05K1/02 ,  H01L25/18 ,  H01L23/538 ,  H01L23/66 ,  H05K1/18

Abstract: Provided is an electronic apparatus capable of improving time margin. The electronic apparatus includes: a base substrate including a substrate base including a plurality of layers and a plurality of wiring layers between the layers; a controller chip and at least one memory semiconductor chip mounted on the base substrate; a signal line disposed in one of the wiring layers and connecting the controller chip to the at least one memory semiconductor chip; and a pair of open stubs disposed in another wiring layer, connected to both ends of the signal line, and extending to face each other with a gap.