公开(公告)号：US20210057411A1

公开(公告)日：2021-02-25

申请号：US16864260

申请日：2020-05-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehyung KIM ,  Jinwoo JEONG ,  Jiwook KWON ,  Raheel AZMAT ,  Kwanyoung CHUN

IPC: H01L27/092 ,  H01L23/528 ,  H01L27/11 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device including a substrate; first to third active patterns on an upper portion of the substrate, the active patterns being sequentially arranged in a first direction and extending in a second direction crossing the first direction; first to third power rails respectively connected to the first to third active patterns, wherein a width of the second active pattern in the first direction is at least two times a width of the first active pattern in the first direction and is at least two times a width of the third active pattern in the first direction, the first active pattern is not vertically overlapped with the first power rail, the second active pattern is vertically overlapped with the second power rail, and the third active pattern is not vertically overlapped with the third power rail.

公开(公告)号：US20200321355A1

公开(公告)日：2020-10-08

申请号：US16574339

申请日：2019-09-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwoo JEONG ,  Jiwook KWON ,  Sutae KIM ,  Hyelim KIM

IPC: H01L27/118 ,  H01L27/02

Abstract: A semiconductor device including first and second active regions extending in a first direction; a field region between the first and second active regions; a gate structure including an upper gate electrode overlapping the first active region and extending in a second direction crossing the first direction, and a lower gate electrode overlapping the second active region, extending in the second direction, and on a same line as the upper gate electrode; a gate isolation layer between the upper and lower gate electrodes; source/drain regions on respective sides of the upper gate electrode; a contact jumper crossing the upper gate electrode in the second active region and electrically connecting the source/drain regions; and a first upper contact extending in the second direction in the field region and overlapping the lower gate electrode and the gate isolation layer, wherein the upper gate electrode is a dummy gate electrode.

公开(公告)号：US20240170402A1

公开(公告)日：2024-05-23

申请号：US18205139

申请日：2023-06-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonggu SIM ,  Jiwook KWON ,  Jinwoo JEONG

IPC: H01L23/528

CPC classification number: H01L23/5286 ,  H01L23/5283

Abstract: A semiconductor device includes logic cells including first conductive lines, first power lines, second conductive lines on the first conductive lines, first power lines, and third conductive lines and second power lines on the second conductive lines. The first conductive line, first power line, third conductive line, and second power line extend in a first direction, the second conductive line extends in a second direction crossing the first direction, the second conductive line includes separation areas near a boundary of the logic cell, the separation areas are alternately positioned at a lower side and an upper side based on the boundary of the logic cell in zigzag form. The first conductive lines and the second conductive lines overlap first hit points to which the first conductive lines and the second conductive lines can be connected, except for a point adjacent to the separation area of the second conductive line.

公开(公告)号：US20220271034A1

公开(公告)日：2022-08-25

申请号：US17740900

申请日：2022-05-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehyung KIM ,  Jinwoo JEONG ,  Jiwook KWON ,  Raheel AZMAT ,  Kwanyoung CHUN

IPC: H01L27/092 ,  H01L23/528 ,  H01L27/11 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/02

Abstract: A semiconductor device including a substrate; first to third active patterns on an upper portion of the substrate, the active patterns being sequentially arranged in a first direction and extending in a second direction crossing the first direction; first to third power rails respectively connected to the first to third active patterns, wherein a width of the second active pattern in the first direction is at least two times a width of the first active pattern in the first direction and is at least two times a width of the third active pattern in the first direction, the first active pattern is not vertically overlapped with the first power rail, the second active pattern is vertically overlapped with the second power rail, and the third active pattern is not vertically overlapped with the third power rail.