公开(公告)号：US11057026B2

公开(公告)日：2021-07-06

申请号：US16831452

申请日：2020-03-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongkyu Ryu ,  Minsu Kim ,  Ahreum Kim ,  Daeseong Lee ,  Hyun Lee

IPC: H03K3/356 ,  H03K3/012 ,  H03K19/20

Abstract: A semi-dynamic flip-flop includes a semiconductor substrate, first through fourth power rails, and at least one clock gate line. The first through fourth power rails are disposed on the semiconductor substrate, extend in a first direction, and are arranged sequentially in a second direction substantially perpendicular to the first direction. The at least one clock gate line is disposed on the semiconductor substrate, and extends in the second direction to pass through at least two regions among a first region between the first power rail and the second power rail, a second region between the second power rail and the third power rail, and a third region between the third power rail and the fourth power rail. The at least one clock gate line receives an input clock signal.