公开(公告)号：US20250126801A1

公开(公告)日：2025-04-17

申请号：US18732848

申请日：2024-06-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju Seong Min ,  Hak Seon Kim ,  Jae-Bok Baek ,  Kang-Oh Yun ,  Taek Kyu Yoon ,  Dong Jin Lee ,  Jae Duk Lee ,  Se Jin Lim ,  Jee Hoon Han

IPC: H10B43/40 ,  H10B43/27

Abstract: The present disclosure relates to semiconductor memory devices. An example semiconductor memory device includes a cell region and a peripheral circuit region electrically connected with the cell region. The cell region includes a plurality of gate electrodes spaced apart from each other and stacked in a vertical direction, and a channel structure extending through the plurality of gate electrodes in the vertical direction. The peripheral circuit region includes a substrate, a first element isolation structure, a first gate structure on the first active region, a second element isolation structure, a second gate structure on the second active region, a third element isolation structure, and a third gate structure on the third active region. The third element isolation structure includes a first element isolation pattern and a second element isolation pattern. The first element isolation pattern and the second element isolation pattern include different materials from each other.