公开(公告)号：US20240412771A1

公开(公告)日：2024-12-12

申请号：US18507444

申请日：2023-11-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiryong Kim ,  Jungmyung Kang ,  Inhak Lee ,  Jaesung Choi ,  Jeonseung Kang ,  Duhwi Kim ,  Jaeyoung Kim

IPC: G11C11/4074 ,  G11C11/4072 ,  G11C11/4096

Abstract: An embedded memory device includes a retention voltage supply circuit outputting a retention voltage in response to a retention activation signal, and a plurality of array voltage supply circuits outputting corresponding array voltages to corresponding bit cells. The plurality of array voltage supply circuits respectively include an array switch providing the retention voltage as a corresponding array voltage in response to the retention activation signal, a power switch providing a power supply voltage as the corresponding array voltage in response to a power gate activation signal, and an auxiliary circuit compensating the corresponding array voltage during a write operation or a read operation.

公开(公告)号：US20250167805A1

公开(公告)日：2025-05-22

申请号：US18764731

申请日：2024-07-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiryong Kim ,  Inhak Lee ,  Jaesung Choi

IPC: H03M13/09 ,  H03M13/00

Abstract: An example column redundancy circuit of a memory device comprises a pre-decoder circuit, a main decoder circuit, and a shift logic circuit. The pre-decoder circuit is configured to receive a lower column address from a plurality of fault column addresses and perform a first decoding operation, and to receive an upper column address from the plurality of fault column address and perform a second decoding operation. The main decoder circuit includes a plurality of main decoders, and each main decoder is configured to receive a lower signal and one or more upper signals from the pre-decoder circuit and to perform a main decoding operation. The shift logic circuit includes a plurality of shift logics, and each shift logic is configured to generate a shift signal that performs a column shift operation according to a result of the main decoding operation.