公开(公告)号：US20180269333A1

公开(公告)日：2018-09-20

申请号：US15981578

申请日：2018-05-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mirco CANTORO ,  Yeon-cheol HEO ,  Maria Toledano LUQUE

IPC: H01L29/786 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423

CPC classification number: H01L29/78696 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/42392 ,  H01L29/78609 ,  H01L29/78618 ,  H01L29/78642

Abstract: An integrated circuit device includes a substrate, first and second fin active regions formed on the substrate and extending in a first direction parallel to a top surface of the substrate, a first gate structure disposed on a side surface of the first fin active region, a pair of first impurity regions respectively formed on a top portion and a bottom portion of the first fin active region, a second gate structure disposed on a side surface of the second fin active region, and a pair of second impurity regions respectively formed on a top portion or a bottom portion of the second fin active region, wherein the pair of first impurity regions vertically overlap each other, and the pair of second impurity regions do not vertically overlap each other.

公开(公告)号：US20180040740A1

公开(公告)日：2018-02-08

申请号：US15598675

申请日：2017-05-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mirco CANTORO ,  Yeon-cheol HEO ,  Maria Toledano LUQUE

IPC: H01L29/786 ,  H01L29/423 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/78696 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/42392 ,  H01L29/78609 ,  H01L29/78618 ,  H01L29/78642

Abstract: An integrated circuit device includes a substrate, first and second fin active regions formed on the substrate and extending in a first direction parallel to a top surface of the substrate, a first gate structure disposed on a side surface of the first fin active region, a pair of first impurity regions respectively formed on a top portion and a bottom portion of the first fin active region, a second gate structure disposed on a side surface of the second fin active region, and a pair of second impurity regions respectively formed on a top portion or a bottom portion of the second fin active region, wherein the pair of first impurity regions vertically overlap each other, and the pair of second impurity regions do not vertically overlap each other.