公开(公告)号：US12272423B2

公开(公告)日：2025-04-08

申请号：US17974940

申请日：2022-10-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sachin Suresh Upadhya ,  Eldho Pathiyakkara Thombra Mathew ,  Mayuresh Jyotindra Salelkar ,  Jinin So ,  Jonggeon Lee ,  Kyungsoo Kim

IPC: G11C7/10 ,  G11C7/22

Abstract: A method of operating a Near Memory Processing-Dual In-line Memory (NMP-DIMM) system, the method including: determining, by an adaptive latency module of the NMP-DIMM system, a synchronized read latency value for performing a read operation upon receiving a Multi-Purpose Register (MPR) read instruction from a host device communicatively connected with the NMP-DIMM system, wherein the MPR read instruction is received from the host device for training the NMP-DIMM system, wherein the synchronized read latency value is determined based on one or more read latency values associated with one or more memory units of the NMP-DIMM system; and synchronizing, by the adaptive latency module, one or more first type data paths and a second type data path in the NMP-DIMM system based on the determined synchronized read latency value.

公开(公告)号：US20230386534A1

公开(公告)日：2023-11-30

申请号：US17974940

申请日：2022-10-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sachin Suresh Upadhya ,  Eldho Pathiyakkara Thombra Mathew ,  Mayuresh Jyotindra Salelkar ,  Jinin So ,  Jonggeon Lee ,  Kyungsoo Kim

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1069 ,  G11C7/1066 ,  G11C7/227 ,  G11C7/1063

Abstract: A method of operating a Near Memory Processing-Dual In-line Memory (NMP-DIMM) system, the method including: determining, by an adaptive latency module of the NMP-DIMM system, a synchronized read latency value for performing a read operation upon receiving a Multi-Purpose Register (MPR) read instruction from a host device communicatively connected with the NMP-DIMM system, wherein the MPR read instruction is received from the host device for training the NMP-DIMM system, wherein the synchronized read latency value is determined based on one or more read latency values associated with one or more memory units of the NMP-DIMM system; and synchronizing, by the adaptive latency module, one or more first type data paths and a second type data path in the NMP-DIMM system based on the determined synchronized read latency value.