Patent search ap:("SAMSUNG ELECTRONICS CO. Page LTD.") AND inv:"Min-Soo Kang"

1.

发明授权
Test pattern, test method for semiconductor device, and computer-implemented designing integrated circuit layout 有权

公开(公告)号：US10572616B2

公开(公告)日：2020-02-25

申请号：US15259673

申请日：2016-09-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Wook Hwang , Jong-Hyun Lee , Min-Soo Kang

IPC: G06F17/50 , H01L21/66

Abstract: A test pattern includes first line patterns disposed at a first level, having discontinuous regions spaced apart by a first space, having a first width, and extending in a first direction. The test pattern includes a connection line pattern disposed at a second level and extending in the first direction, second line patterns disposed at the second level, branching from the connection line pattern, having a second width, and extending in a second direction perpendicular to the first direction. The test pattern includes via patterns disposed at a third level, having a third width, and formed around an intersection region having the first width of the first line pattern and the second width of the second line pattern. First pads are connected with the first line patterns. A second pad is connected with the connection line pattern.

2.

发明授权
Test pattern, test method for semiconductor device, and computer-implemented method for designing integrated circuit layout 有权

公开(公告)号：US10885244B2

公开(公告)日：2021-01-05

申请号：US16739624

申请日：2020-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Wook Hwang , Jong-Hyun Lee , Min-Soo Kang

IPC: G06F30/30 , H01L21/66

Abstract: A test pattern includes first line patterns disposed at a first level, having discontinuous regions spaced apart by a first space, having a first width, and extending in a first direction. The test pattern includes a connection line pattern disposed at a second level and extending in the first direction, second line patterns disposed at the second level, branching from the connection line pattern, having a second width, and extending in a second direction perpendicular to the first direction. The test pattern includes via patterns disposed at a third level, having a third width, and formed around an intersection region having the first width of the first line pattern and the second width of the second line pattern. First pads are connected with the first line patterns. A second pad is connected with the connection line pattern.

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