公开(公告)号：US20220147680A1

公开(公告)日：2022-05-12

申请号：US17095937

申请日：2020-11-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： NIV ZEHNGUT ,  AMIR BEN-DROR ,  EVGENY ARTYOMOV ,  MICHAEL DINERSTEIN ,  ROY JEVNISEK

IPC: G06F30/39 ,  G06N3/04 ,  G06N3/08

Abstract: Methods, systems, and apparatus for combined or separate implementation of coarse-to-fine neural architecture search (NAS), two-phase block NAS, variable hardware prediction, and differential hardware design are provided and described. A variable predictor is trained, as described herein. Then, a controller or policy may be used to iteratively modify a neural network architecture along dimensions formed by neural network architecture parameters. The modification is applied to blocks (e.g., subnetworks) within the neural network architecture. In each iteration, the remainder of the neural network architecture parameters are modified and learned with a differential NAS method. The training process is performed with two-phase block NAS and incorporates a variable hardware predictor to predict power, performance, and area (PPA) parameters. The hardware parameters may be learned as well using the variable hardware predictor.