公开(公告)号：US20210358935A1

公开(公告)日：2021-11-18

申请号：US17095821

申请日：2020-11-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KWANGYOUNG JUNG ,  SANGYOUN JO ,  KOHJI KANAMORI ,  JEEHOON HAN

IPC: H01L27/11573 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11519 ,  G11C16/08 ,  H01L27/11534 ,  G11C7/18

Abstract: A 3D semiconductor memory device includes a peripheral circuit structure including a first row decoder region, a second row decoder region, and a control circuit region between the first and second row decoder regions, a first electrode structure and a second electrode structure on the peripheral circuit structure, spaced apart in a first direction, and each including stacked electrodes, a mold structure on the peripheral circuit structure between the first and second electrode structures and including stacked sacrificial layers, vertical channel structures penetrating the first and second electrode structures, a separation insulating pattern provided between the first electrode structure and the mold structure and penetrating the mold structure, and a separation structure intersecting the first electrode structure in the first direction and extending to the separation insulating pattern, wherein a maximum width of the separation insulating pattern in a second direction is greater than a maximum width of the separation structure in the second direction.

公开(公告)号：US20230076039A1

公开(公告)日：2023-03-09

申请号：US17983024

申请日：2022-11-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KWANGYOUNG JUNG ,  SANGYOUN JO ,  KOHJI KANAMORI ,  JEEHOON HAN

IPC: H01L27/11573 ,  H01L27/11556 ,  H01L27/11582 ,  G11C7/18 ,  H01L27/11519 ,  G11C16/08 ,  H01L27/11534 ,  H01L27/11565

Abstract: A 3D semiconductor memory device includes a peripheral circuit structure including a first row decoder region, a second row decoder region, and a control circuit region between the first and second row decoder regions, a first electrode structure and a second electrode structure on the peripheral circuit structure, spaced apart in a first direction, and each including stacked electrodes, a mold structure on the peripheral circuit structure between the first and second electrode structures and including stacked sacrificial layers, vertical channel structures penetrating the first and second electrode structures, a separation insulating pattern provided between the first electrode structure and the mold structure and penetrating the mold structure, and a separation structure intersecting the first electrode structure in the first direction and extending to the separation insulating pattern, wherein a maximum width of the separation insulating pattern in a second direction is greater than a maximum width of the separation structure in the second direction.