公开(公告)号：US20210117755A1

公开(公告)日：2021-04-22

申请号：US17033132

申请日：2020-09-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gopinath Vasanth Mahale ,  Pramod Parameshwara Udupa ,  Kiran Kolar Chandrasekharan ,  SEHWAN LEE

IPC: G06N3/04

Abstract: Disclosed is a hybrid traversal apparatus and method for a convolution neural network (CNN) accelerator architecture that receives input feature map (IFM) microbatches from a pixel memory and receiving kernel microbatches from a kernel memory, multiplies the IFM microbatches by the kernel microbatches while reusing the kernel microbatches based on a kernel reuse factor for at least one of a direct convolution (DConv) or a Winograd convolution (WgConv), to obtain output feature map (OFM) microbatches, and writes the generated OFM microbatches to the pixel memory, after quantization, non-linear function, and pooling on a result of the multiplying.

公开(公告)号：US20190146926A1

公开(公告)日：2019-05-16

申请号：US16012808

申请日：2018-06-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEHWAN LEE ,  HYUN JIN CHOI

IPC: G06F12/10

Abstract: A storage device includes a memory device and a controller that translates a logical address received from a host into a physical address for the memory device. The controller manages correspondence information indicating a correspondence relationship between logical addresses and physical addresses and a mapping function for determining a mapping unit corresponding to the received logical address in a partial memory area on the memory device indicated by a physical address managed in the correspondence information. The mapping unit corresponding to the received logical address is an area on the memory device indicated by the received logical address. The controller determines the partial memory area including the mapping unit corresponding to the received logical address with reference to the correspondence information and determines the mapping unit from the partial memory area by using the mapping function.