公开(公告)号：US20240251544A1

公开(公告)日：2024-07-25

申请号：US18474394

申请日：2023-09-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEUNGMIN SHIN ,  SANGJUN PARK ,  SUNGJOO AN ,  KIJONG PARK ,  ILYOUNG YOON

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/05

Abstract: A semiconductor memory device according to an embodiment includes: a substrate; a bit line positioned on the substrate and extending in a first direction; a channel accommodating insulating layer positioned on the substrate, and defining a channel trench exposing the bit line and extending in a second direction crossing the first direction; a channel layer extending along a bottom surface and a side surface of the channel trench and contacting the bit line; a word line positioned in the channel trench and extending in the second direction; a gate insulating layer positioned between the channel layer and the word line; and a capacitor structure positioned on the channel layer and electrically connected to the channel layer, in which the channel layer has a double layer structure of an oxide semiconductor layer and a first graphene layer.