公开(公告)号：US20230411451A1

公开(公告)日：2023-12-21

申请号：US18182435

申请日：2023-03-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEUNG MO KANG ,  TAEGON KIM ,  JAEMUN KIM ,  JAEHOON OH ,  SUNHYE LEE ,  SIHYUNG LEE ,  JURI LEE

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/02 ,  H01L21/768 ,  H01L29/423

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L21/02164 ,  H01L21/76829 ,  H01L29/42392

Abstract: A semiconductor device may include a first active pattern and a second active pattern on a substrate, a device isolation layer in a trench between the first active pattern and the second active pattern, a first channel pattern and a second channel pattern provided on the first active pattern and the second active pattern, respectively, each of the first channel pattern and the second channel pattern including a plurality of stacked semiconductor patterns, and a gate electrode on the first channel pattern and the second channel pattern. The device isolation layer may include a first portion and a second portion which are vertically overlapped with the gate electrode. The first portion may be provided on the second portion. A silicon concentration of the first portion may be higher than a silicon concentration of the second portion.