-
公开(公告)号：US20240184526A1
公开(公告)日：2024-06-06
申请号：US18329045
申请日：2023-06-05
发明人： Seungwoo SEO , Sanghoon CHA
CPC分类号： G06F7/5443 , G06F7/502 , G06F9/30145
摘要： A memory device includes: a plurality of memory banks divided by a plurality of channels comprising a first channel and a second channel; and a channel-level processing element (PE) configured to generate an in-memory computation result by performing an operation using a first partial result generated based on data stored in a memory bank of the first channel among the plurality of memory banks and a second partial result generated based on data stored in a memory bank of the second channel among the plurality of memory banks.
-
公开(公告)号：US20240257851A1
公开(公告)日：2024-08-01
申请号：US18499551
申请日：2023-11-01
发明人： Sanghoon CHA , Yuhwan RO , Seungwoo SEO
CPC分类号： G11C8/06 , G11C7/1063 , G11C8/04
摘要： A memory device includes: a memory bank module comprising a memory bank; and an operation module comprising a processing in memory (PIM) block, wherein the memory bank comprises: an array of memory cells arranged in a plurality of rows and a plurality of columns; a row buffer configured to store data of a row corresponding to a row address among the plurality of rows; and a selecting module configured to select first data and second data corresponding to a column address from among the data stored in the row buffer, wherein the first data is transmitted to the PIM block through a first data path connected between the selecting module and the PIM block, and the second data is transmitted to the PIM block through a second data path connected between the selecting module and the PIM block.
-
搜索结果
2 条记录 (耗时 0.014 秒)
