公开(公告)号：US20240404935A1

公开(公告)日：2024-12-05

申请号：US18662240

申请日：2024-05-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seunghun Chae ,  Unbyoung Kang

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L25/10

Abstract: A semiconductor package includes a redistribution structure that includes a lower insulating layer, redistribution layers in the lower insulating layer, and first vias connected to the redistribution layers. The semiconductor package further includes a semiconductor chip on an upper surface of the redistribution structure and electrically connected to the redistribution layers; an interconnection structure on the upper surface of the redistribution structure and including an upper insulating layer, a plurality of interconnection layers, and second vias connecting the interconnection layers to each other; an encapsulant covering the semiconductor chip and the interconnection structure; and external connection conductors on a lower surface of the redistribution structure and electrically connected to the redistribution layers. A lowermost interconnection layer includes a first conductive layer contacting a second via and tapered toward the upper surface, and a second conductive layer surrounding the first conductive layer and in contact with a first via.

公开(公告)号：US11417595B2

公开(公告)日：2022-08-16

申请号：US16991306

申请日：2020-08-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seunghun Chae ,  Youngkwan Seo ,  Jaeean Lee ,  Soyeon Moon ,  Hyeyeong Jo ,  Iljong Seo

IPC: H01L23/495 ,  H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H01L23/367 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package includes a redistribution substrate having first and second surfaces, and an insulating member and a plurality of redistribution layers on different levels in the insulating member and electrically connected together; a plurality of under bump metallurgy (UBM) pads in the insulating member and connected to a redistribution layer, among the plurality of redistribution layers, adjacent to the first surface, the UBM pads having a lower surface exposed to the first surface of the redistribution substrate; a dummy pattern between the UBM pads in the insulating member, the dummy pattern having a lower surface located at a level higher than the lower surface of the UBM pads; and at least one semiconductor chip on the second surface of the redistribution substrate and having a plurality of contact pads electrically connected to a redistribution layer, among the plurality of redistribution layers, adjacent to the second surface.