公开(公告)号：US20240232004A9

公开(公告)日：2024-07-11

申请号：US18400256

申请日：2023-12-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungwon JEONG ,  Moonsang KWON ,  Younghoi HEO ,  Jaeshin LEE ,  Eun JUNG

IPC: G06F11/10 ,  G06N20/00

CPC classification number: G06F11/1004 ,  G06N20/00

Abstract: A storage device and an operating method thereof are provided. The storage device includes a non-volatile memory and a storage controller. The storage controller includes a command and address generator, an error detection module, and an interface circuit. The command and address generator generates a first command, an address, and a second command, the second command including an error detection signal for detecting a communication error in the first command and the address. The error detection module generates the error detection signal from the first command and the address. The interface circuit sequentially transmits the first command, the address, and the second command to the non-volatile memory. The first command indicates a type of a memory operation to be performed in the non-volatile memory, and the second command corresponds to a confirm command.

公开(公告)号：US20240134741A1

公开(公告)日：2024-04-25

申请号：US18400256

申请日：2023-12-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungwon JEONG ,  Moonsang KWON ,  Younghoi HEO ,  Jaeshin LEE ,  Eun JUNG

IPC: G06F11/10 ,  G06N20/00

CPC classification number: G06F11/1004 ,  G06N20/00

Abstract: A storage device and an operating method thereof are provided. The storage device includes a non-volatile memory and a storage controller. The storage controller includes a command and address generator, an error detection module, and an interface circuit. The command and address generator generates a first command, an address, and a second command, the second command including an error detection signal for detecting a communication error in the first command and the address. The error detection module generates the error detection signal from the first command and the address. The interface circuit sequentially transmits the first command, the address, and the second command to the non-volatile memory. The first command indicates a type of a memory operation to be performed in the non-volatile memory, and the second command corresponds to a confirm command.