公开(公告)号：US20240095113A1

公开(公告)日：2024-03-21

申请号：US18232442

申请日：2023-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： TAESUN KIM ,  JINHONG PARK ,  HWISOO SO ,  KYOUNGWOO LEE ,  JINHYO JUNG

IPC: G06F11/07 ,  G06F9/38

CPC classification number: G06F11/0751 ,  G06F9/3867

Abstract: A processor includes an instruction pipeline that sequentially processes an original instruction and a duplicate instruction, which is generated by duplicating the original instruction. An original register file stores a result obtained by processing the original instruction in the instruction pipeline within a register of a nth index thereof. A duplicate register file stores a result obtained by processing the duplicate instruction in the instruction pipeline within a register of a nth index thereof. A comparing unit compares the register of the nth index in the original register file with the register of nth index in the duplicate register file and outputs an error detection signal, in response to a control signal.