公开(公告)号：US20240251545A1

公开(公告)日：2024-07-25

申请号：US18493924

申请日：2023-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Seong PARK ,  Seung Hee LEE ,  Yong-Suk TAK ,  Dong-Gyu KIM ,  Yu Rim KIM ,  Tae Won KIM ,  Dong-Hyeon LEE

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/05

Abstract: There is provided a semiconductor memory device having improved integration and electrical characteristics. The semiconductor memory device includes a bit line extending in a first direction on a substrate, a first channel pattern disposed on the bit line, a second channel pattern disposed on the bit line and spaced apart from the first channel pattern in the first direction, a first word line disposed between the first channel pattern and the second channel pattern extends in a second direction, a second word line disposed between the first channel pattern and the second channel pattern, extends in the second direction, and is spaced apart from the first word line in the first direction, and a first capacitor and a second capacitor disposed on and connected to the first channel pattern and the second channel pattern, respectively, wherein each of the first channel pattern and the second channel pattern includes a first metal oxide pattern including indium (In), gallium (Ga) and tin (Sn), and a position of a peak of tin is different from a position of a peak of gallium in a spatial composition distribution of the first metal oxide pattern.

公开(公告)号：US20250103217A1

公开(公告)日：2025-03-27

申请号：US18743324

申请日：2024-06-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae Won KIM ,  Jun Myung WOO

IPC: G06F3/06 ,  G11C11/406

Abstract: A memory device includes a memory cell array including memory cell rows, a first random number generator generating an n-bit first pseudo random bit sequence signal based on a first seed and a first degree, first and second memory cell row picking circuits, and a refresh control circuit. The first memory cell row picking circuit randomly selects a first memory cell row at a first cycle, and stores a row address of the selected first memory cell row in a first queue. The second memory cell row picking circuit randomly selects a second memory cell row at a second cycle, and stores a row address of the selected second memory cell row in a second queue. The refresh control circuit performs a refresh operation on memory cell rows physically adjacent to memory cell rows corresponding to each of the row addresses stored in the first queue and the second queue.