公开(公告)号：US20200328227A1

公开(公告)日：2020-10-15

申请号：US16787195

申请日：2020-02-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JIN-KYU KANG ,  WOOJAE JANG ,  CHANGSUB LEE ,  SEJUN PARK ,  JAEDUK LEE ,  JUNG HOON LEE

IPC: H01L27/11582 ,  H01L29/423 ,  H01L29/792

Abstract: A three-dimensional semiconductor memory device including a stack structure including gate structures and first dielectric patterns alternately stacked, a vertical channel penetrating the stack structure, and a charge storage layer extending from between the vertical channel and the first gate structures to between the vertical channel and the first dielectric patterns. The gate structures include first gate structures having a top surface and a bottom surface facing each other and having different width. The charge storage layer includes first segments between the vertical channel and the first gate structures, and second segments between the vertical channel and the first dielectric patterns. A thickness of the first segments is greater than a thickness of the second segments. One of the width of the top surface and the width of bottom surface of each first gate structure is the same as that of a first dielectric pattern on the first gate structure.

公开(公告)号：US20200303015A1

公开(公告)日：2020-09-24

申请号：US16898533

申请日：2020-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNYEONG LEE ,  KYUNGMOON KIM ,  WOOJAE JANG ,  CHANJONG JU

IPC: G11C16/16 ,  H01L27/11582 ,  H01L27/1157 ,  G11C16/34 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/04

Abstract: A nonvolatile memory device includes a memory cell array, an erase body voltage generator, and an erase source voltage generator. The memory cell array includes memory blocks, each of which includes cell strings each including a ground selection transistor, memory cells, and a string selection transistor stacked in a direction perpendicular to a substrate. The erase body voltage generator applies an erase body voltage to the substrate during an erase operation. The erase source voltage generator applies an erase source voltage to a common source line connected with ground selection transistors of the cell strings during the erase operation.

公开(公告)号：US20190279719A1

公开(公告)日：2019-09-12

申请号：US16177479

申请日：2018-11-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNYEONG LEE ,  KYUNGMOON KIM ,  WOOJAE JANG ,  CHANJONG JU

IPC: G11C16/16 ,  H01L27/11582 ,  H01L27/1157 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/34

Abstract: A nonvolatile memory device includes a memory cell array, an erase body voltage generator, and an erase source voltage generator. The memory cell array includes memory blocks, each of which includes cell strings each including a ground selection transistor, memory cells, and a string selection transistor stacked in a direction perpendicular to a substrate. The erase body voltage generator applies an erase body voltage to the substrate during an erase operation. The erase source voltage generator applies an erase source voltage to a common source line connected with ground selection transistors of the cell strings during the erase operation.