公开(公告)号：US09361661B2

公开(公告)日：2016-06-07

申请号：US14017422

申请日：2013-09-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Kon Bae ,  Dokyung Kim ,  Wonsik Kang

IPC: G06T1/60 ,  G09G5/00 ,  G09G5/399

CPC classification number: G06T1/60 ,  G09G5/006 ,  G09G5/399 ,  G09G2370/10

Abstract: A display driver integrated circuit is provided which includes a first line buffer which receives first pixel data of an odd lane in response to an external clock and outputs the first pixel data in response to an internal clock; a second line buffer which receives second pixel data of an even lane in response to the external clock and outputs the second pixel data in response to the internal clock; a line buffer controller which receives display data by the two pixel data to output the first and second pixel data; a data merger which merges the first pixel data output from the first line buffer and second pixel data output from the second line buffer; and an image data processing block which processes the merged pixel data, wherein a frequency of the internal clock is lower than a frequency of the external clock.

Abstract translation: 提供一种显示驱动器集成电路，其包括响应于外部时钟接收奇数通道的第一像素数据的第一行缓冲器，并响应于内部时钟输出第一像素数据; 第二行缓冲器，其响应于外部时钟接收偶数行的第二像素数据，并响应于内部时钟输出第二像素数据; 线缓冲器控制器，其通过两个像素数据接收显示数据以输出第一和第二像素数据; 合并从第一行缓冲器输出的第一像素数据和从第二行缓冲器输出的第二像素数据的数据合并; 以及处理合并像素数据的图像数据处理块，其中内部时钟的频率低于外部时钟的频率。