公开(公告)号：US12113545B2

公开(公告)日：2024-10-08

申请号：US17872173

申请日：2022-07-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yanghoon Lee ,  Wan Kim

IPC: H03M1/12 ,  H03M1/68 ,  H03M1/80

CPC classification number: H03M1/802 ,  H03M1/68

Abstract: A capacitor digital-to-analog converter (CDAC) includes a clock generator, a random reset control signal generator, a first capacitor array, a first reset circuit and an output buffer. The clock generator generates an internal clock signal and a reset control signal that are regularly toggled. The random reset control signal generator generates a random reset control signal that is irregularly toggled. The first capacitor array includes a plurality of capacitors connected to a first summation node, and generates a first summation voltage corresponding to a first input digital signal based on first and second reference voltages. The first reset circuit initializes the first summation node based on the random reset control signal. The output buffer generates a first analog output voltage by buffering the first summation voltage.