公开(公告)号：US20250068517A1

公开(公告)日：2025-02-27

申请号：US18944088

申请日：2024-11-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunhye OH ,  Taewook PARK ,  Jisu KANG ,  Yongki LEE

IPC: G06F11/10 ,  G06F11/07

Abstract: Provided is a storage device including a memory device configured to store original data; and a controller configured to control the memory device, the controller including a first error correction circuit configured to correct an error of the original data, and a second error correction circuit configured to correct an error of the original data, a maximum number of correctable error bits of the second error correction circuit being greater than a maximum number of correctable error bits of the first error correction circuit, a mapping memory configured to store at least some of parity bits generated by the second error correction circuit and store an address of the memory device at which the original data is stored; and a control block configured to control the first error correction circuit, the second error correction circuit, and the mapping memory.

公开(公告)号：US20230214297A1

公开(公告)日：2023-07-06

申请号：US18148061

申请日：2022-12-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunhye OH ,  Taewook PARK ,  Jisu KANG ,  Yongki LEE

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/1068 ,  G06F11/076 ,  G06F11/1004

Abstract: Provided is a storage device including a memory device configured to store original data; and a controller configured to control the memory device, the controller including a first error correction circuit configured to correct an error of the original data, and a second error correction circuit configured to correct an error of the original data, a maximum number of correctable error bits of the second error correction circuit being greater than a maximum number of correctable error bits of the first error correction circuit, a mapping memory configured to store at least some of parity bits generated by the second error correction circuit and store an address of the memory device at which the original data is stored; and a control block configured to control the first error correction circuit, the second error correction circuit, and the mapping memory.

公开(公告)号：US20230025153A1

公开(公告)日：2023-01-26

申请号：US17867150

申请日：2022-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yunhyeok CHOI ,  Yongki LEE ,  Sumin NOH ,  Jieun PARK ,  Bohdan KARPINSKYY

IPC: G06F7/58

Abstract: A random number generating circuit includes: an oscillation circuit including a plurality of first delay elements connected to each other in series to generate an oscillation signal; a sampling circuit including a plurality of second delay elements connected to each other in series to generate a plurality of sampling signals by sampling the oscillation signal at a plurality of sampling points in time based on the plurality of second delay elements; and a random number determining circuit configured to generate a random number based on a target sampling point in time associated with a target sampling signal in which a first logic level transition occurs from among the plurality of sampling signals, wherein the plurality of sampling points includes the target sampling point.