公开(公告)号：US20220100669A1

公开(公告)日：2022-03-31

申请号：US17403862

申请日：2021-08-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeok Jun Choe ,  Youn Ho Jeon ,  Young Geon Yoo ,  Hyo-Deok Shin ,  I Poom Jeong

IPC: G06F12/0877 ,  G06F13/28

Abstract: A smart storage device is provided. The smart storage device includes a smart interface connected to a host device. An accelerator circuit is connected to the smart interface through a data bus conforming to a CXL.cache protocol and a CXL.mem protocol. The accelerator circuit is configured to perform acceleration computation in response to a computation command of the host device. A storage controller is connected to the smart interface through a data bus conforming to a CXL.io protocol. The storage controller is configured to control a data access operation for a storage device in response to a data access command of the host device. The accelerator circuit is directly accessible to the storage device through an internal bus connected directly to the storage controller.

公开(公告)号：US11360666B2

公开(公告)日：2022-06-14

申请号：US16862267

申请日：2020-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung Hyun Hong ,  Young Jin Cho ,  Hyeok Jun Choe ,  Young Geon Yoo ,  Chan Ho Yoon

IPC: G06F3/06

Abstract: A storage controller includes a host interface which real-time analyzes a command received from a host, a programmable logic unit which loads an optimal image adaptively selected from a plurality of images in response to at least one of a current operating state of the storage controller and the command, and a processor which performs an operation on a nonvolatile memory device using the programmable logic unit after the optimal image is loaded.

公开(公告)号：US12259817B2

公开(公告)日：2025-03-25

申请号：US17403862

申请日：2021-08-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeok Jun Choe ,  Youn Ho Jeon ,  Young Geon Yoo ,  Hyo-Deok Shin ,  I Poom Jeong

IPC: G06F12/0877 ,  G06F13/28

Abstract: A smart storage device is provided. The smart storage device includes a smart interface connected to a host device. An accelerator circuit is connected to the smart interface through a data bus conforming to a CXL.cache protocol and a CXL.mem protocol. The accelerator circuit is configured to perform acceleration computation in response to a computation command of the host device. A storage controller is connected to the smart interface through a data bus conforming to a CXL.io protocol. The storage controller is configured to control a data access operation for a storage device in response to a data access command of the host device. The accelerator circuit is directly accessible to the storage device through an internal bus connected directly to the storage controller.