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公开(公告)号：US20210294376A1
公开(公告)日：2021-09-23
申请号：US17338320
申请日：2021-06-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： YOUNG-JIN CHO , Jae-Geun Park , Young-Kwang Yoo , Soon-Suk Hwang
Abstract: A memory system including a memory controller with channel interfaces connecting memory groups via channels. Each channel interface communicates control, address and/or data (CAD) signals to a channel-connected memory group synchronously with a slave clock derived from an input clock. The various slave clocks being uniquely generated by application of channel interface specific phase/frequency modulation or temporal delay, such that the respective CAD signals are characterized by skewed transition timing.
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公开(公告)号：US20190033909A1
公开(公告)日：2019-01-31
申请号：US16149987
申请日：2018-10-02
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： YOUNG-JIN CHO , Jae-Geun Park , Young-Kwang Yoo , Soon-Suk Hwang
Abstract: A memory system including a memory controller with channel interfaces connecting memory groups via channels. Each channel interface communicates control, address and/or data (CAD) signals to a channel-connected memory group synchronously with a slave clock derived from an input clock. The various slave clocks being uniquely generated by application of channel interface specific phase/frequency modulation or temporal delay, such that the respective CAD signals are characterized by skewed transition timing.
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公开(公告)号：US11625063B2
公开(公告)日：2023-04-11
申请号：US17338320
申请日：2021-06-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Young-Jin Cho , Jae-Geun Park , Young-Kwang Yoo , Soon-Suk Hwang
Abstract: A memory system including a memory controller with channel interfaces connecting memory groups via channels. Each channel interface communicates control, address and/or data (CAD) signals to a channel-connected memory group synchronously with a slave clock derived from an input clock. The various slave clocks being uniquely generated by application of channel interface specific phase/frequency modulation or temporal delay, such that the respective CAD signals are characterized by skewed transition timing.
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公开(公告)号：US11054855B2
公开(公告)日：2021-07-06
申请号：US16149987
申请日：2018-10-02
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Young-Jin Cho , Jae-Geun Park , Young-Kwang Yoo , Soon-Suk Hwang
Abstract: A memory system including a memory controller with channel interfaces connecting memory groups via channels. Each channel interface communicates control, address and/or data (CAD) signals to a channel-connected memory group synchronously with a slave clock derived from an input clock. The various slave clocks being uniquely generated by application of channel interface specific phase/frequency modulation or temporal delay, such that the respective CAD signals are characterized by skewed transition timing.
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