公开(公告)号：US12175208B2

公开(公告)日：2024-12-24

申请号：US16989391

申请日：2020-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinook Song ,  Daekyeung Kim ,  Junseok Park ,  Joonho Song ,  Sehwan Lee ,  Junwoo Jang ,  Yunkyo Cho

IPC: G06F7/544 ,  G06N3/063

Abstract: An arithmetic apparatus includes a first operand holding circuit configured to output a first operand according to a clock signal, generate an indicator signal based on bit values of high-order bit data including a most significant bit of the first operand, and gate the clock signal based on the indicator signal, the clock signal being applied to a flip-flop latching the high-order bit data of the first operand; a second operand holding circuit configured to output a second operand according to the clock signal; and an arithmetic circuit configured to perform data gating on the high-order bit data of the first operand based on the indicator signal and output an operation result by performing an operation using a modified first operand resulting from the data gating and the second operand.