公开(公告)号：US20210111070A1

公开(公告)日：2021-04-15

申请号：US16785732

申请日：2020-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae Yong BAE ,  Hoon Seok SEO ,  Ki Hyun PARK ,  Hak-Sun LEE

IPC: H01L21/768

Abstract: Integrated circuit devices and methods of forming the same are provided. The methods of forming an integrated circuit device may include forming a first insulating layer and a via contact on a substrate. The substrate may include an upper surface facing the via contact, and the via contact may be in the first insulating layer and may include a lower surface facing the substrate and an upper surface opposite to the lower surface. The methods may also include forming a second insulating layer and a metallic wire on the via contact. The metallic wire may be in the second insulating layer and may include a lower surface that faces the substrate and contacts the upper surface of the via contact. Both the lower surface of the metallic wire and an interface between the metallic wire and the via contact may have a first width in a horizontal direction that is parallel to the upper surface of the substrate.

公开(公告)号：US20150162247A1

公开(公告)日：2015-06-11

申请号：US14531987

申请日：2014-11-03

Applicant: SAMSUNG ELECTRONICS CO., Ltd.

Inventor： Yong-Joon CHOI ,  MYEONGCHEOL KIM ,  CHEOL KIM ,  GeumJung SEONG ,  Hak-Sun LEE ,  Haegeon JUNG ,  Ji-Eun HAN

IPC: H01L21/8234 ,  H01L21/762 ,  H01L21/308 ,  H01L27/088

CPC classification number: H01L21/823431 ,  H01L21/3081 ,  H01L21/76224 ,  H01L27/0886

Abstract: The disclosure provides semiconductor devices and methods of manufacturing the same. The method includes etching a substrate using a first mask pattern formed on the substrate to form a trench, forming a preliminary device isolation pattern filling the trench and including first and second regions having first thicknesses, forming a second mask pattern on the first region, etching an upper portion of the second region and a portion of the first mask pattern, which are exposed by the second mask pattern, to form a second region having a second thickness smaller than the first thickness, removing the first and second mask patterns, and etching upper portions of the first region and the second region having the second thickness to form a device isolation pattern defining preliminary fin-type active patterns. An electronic device including a semiconductor device and a manufacturing method thereof are also disclosed.

Abstract translation: 本公开提供半导体器件及其制造方法。 该方法包括使用形成在衬底上的第一掩模图案来蚀刻衬底以形成沟槽，形成填充沟槽的初步器件隔离图案，并且包括具有第一厚度的第一和第二区域，在第一区域上形成第二掩模图案，蚀刻 第二区域的上部和第一掩模图案的一部分被第二掩模图案曝光，以形成具有小于第一厚度的第二厚度的第二区域，去除第一和第二掩模图案，以及蚀刻 所述第一区域的上部和所述第二区域具有第二厚度，以形成限定预备鳍型活性图案的器件隔离图案。 还公开了一种包括半导体器件及其制造方法的电子器件。