公开(公告)号：US12288719B2

公开(公告)日：2025-04-29

申请号：US17659057

申请日：2022-04-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takuya Maehara

IPC: H01L21/78 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: A method includes forming an etch stop material layer and a planar sacrificial spacer layer over a front surface of a first substrate, forming an insulating encapsulation layer over the planar sacrificial spacer layer and on a backside surface and a side surface of the first substrate, forming a continuous structure including first semiconductor devices over a top surface of the insulating encapsulation layer, etching inter-die trenches within the continuous structure to divide the continuous structure, bonding the divided continuous structure to second semiconductor devices located over a second substrate, selectively removing the planar sacrificial spacer layer by performing a wet etch process in which an isotropic etchant is introduced into the inter-die trenches, and detaching the first substrate from an assembly of the second substrate, the second semiconductor devices, and the divided continuous structure after the removing the planar sacrificial spacer layer.