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公开(公告)号：US20220217480A1
公开(公告)日：2022-07-07
申请号：US17143324
申请日：2021-01-07
摘要： Hearing instruments, such as hearing aids, may improve a quality of presented audio through the use of a binaural application, such as beamforming. The binaural application may require communication between the hearing instruments so that audio from a left hearing instrument may be combined with audio from a right hearing instrument. The combining at a hearing instrument can require synchronizing audio sampled locally with sampled audio received from wireless communication. This synchronization may cause a noticeable delay of an output of the binaural application if the latency of the wireless communication is not low (e.g., a few samples of delay). Presented herein is a low-latency communication protocol that communicates packets on a sample-by-sample basis and that compensates for delays caused by overhead protocol data transmitted with the audio data.
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公开(公告)号：US20190340493A1
公开(公告)日：2019-11-07
申请号：US16385192
申请日：2019-04-16
摘要： A neural network implementation is disclosed. The implementation allows the computations for the neural network to be performed on either an accelerator or a processor. The accelerator and the processor share a memory and communicate over a bus to perform the computations and to share data. The implementation uses weight compression and pruning, as well as parallel processing, to reduce computing, storage, and power requirements.
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公开(公告)号：US20210287074A1
公开(公告)日：2021-09-16
申请号：US16816453
申请日：2020-03-12
发明人： Ivo Leonardus COENEN
IPC分类号： G06N3/063 , G06N3/08 , G11C11/4063
摘要： According to an aspect, a neural network circuit for decoding weights of a neural network includes a weight memory configured to store encoded weights for the neural network, where the encoded weights includes an index weight word, and a decompression logic circuit configured to retrieve the encoded weights from the weight memory, decode the encoded weights using the index weight word to obtain a sequence of one or more non-pruned weight words and one or more pruned weight words, and provide the sequence of the non-pruned weight words and the pruned weight words to a plurality of input-weight multipliers.
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公开(公告)号：US20180139550A1
公开(公告)日：2018-05-17
申请号：US15868142
申请日：2018-01-11
CPC分类号： H04R29/00 , H03G1/0029 , H03G7/007 , H04R25/43 , H04R2201/028 , H04R2460/01
摘要： An electronic system, in some embodiments, comprises: a power source; a load coupled to the power source; an analog-to-digital converter, coupled to the power source and the load, that samples a fluctuating voltage supplied by the power source and generates a digital representation of said fluctuating voltage; control logic, coupled to the analog-to-digital converter, that generates an amplitude correction signal based on said digital representation of the fluctuating voltage and on a target voltage; correction logic, coupled to the control logic, that uses the amplitude correction signal and an audio signal to generate a switch control signal; and an output driver, coupled to the correction logic, that controls coupling between the power source and the load based on the switch control signal.
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5.发明申请公开(公告)号：US20230053440A1
公开(公告)日：2023-02-23
申请号：US17820007
申请日：2022-08-16
发明人： Ivo Leonardus COENEN
摘要： In some aspects, the techniques described herein relate to a system on a chip (SoC) including a first clock divider configured to: receive an oscillator signal at a first frequency; produce, based on the oscillator signal: a first clock signal at the first frequency; and a second clock signal at a second frequency, the second frequency being a division of the first frequency. The first clock divider can selectively provide the first clock signal or the second clock signal as a first output clock signal based on a scaling configuration signal. The first clock divider can produce a frequency indication signal indicating, in combination with the first output clock signal, a start of a new clock period of the second clock signal. The SoC can include a second clock divider configured to provide a second clock output signal based on the first output clock signal and the frequency indication signal.
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公开(公告)号：US20230007414A1
公开(公告)日：2023-01-05
申请号：US17931747
申请日：2022-09-13
摘要： Hearing instruments, such as hearing aids, may improve a quality of presented audio through the use of a binaural application, such as beamforming. The binaural application may require communication between the hearing instruments so that audio from a left hearing instrument may be combined with audio from a right hearing instrument. The combining at a hearing instrument can require synchronizing audio sampled locally with sampled audio received from wireless communication. This synchronization may cause a noticeable delay of an output of the binaural application if the latency of the wireless communication is not low (e.g., a few samples of delay). Presented herein is a low-latency communication protocol that communicates packets on a sample-by-sample basis and that compensates for delays caused by overhead protocol data transmitted with the audio data.
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公开(公告)号：US20210273560A1
公开(公告)日：2021-09-02
申请号：US16948901
申请日：2020-10-05
发明人： Ivo Leonardus COENEN
摘要： Power management for an integrated circuit. At least one example embodiment is a method of operating an integrated circuit on a semiconductor substrate, the method comprising: measuring, by a body voltage controller, a signal indicative of power consumption of devices on the semiconductor substrate, the body voltage controller implemented on the semiconductor substrate; creating, by the body voltage controller, a value indicative of a modified body voltage, the creating based on the signal indicative of power consumption; and modifying, by a body voltage converter on the semiconductor substrate, a body voltage applied to a plurality of transistors on the semiconductor substrate, the modification responsive to the value indicative of the modified body voltage.
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公开(公告)号：US20180054684A1
公开(公告)日：2018-02-22
申请号：US15242358
申请日：2016-08-19
CPC分类号： H04R29/00 , H03G1/0029 , H03G7/007 , H04R25/43 , H04R2201/028 , H04R2460/01
摘要： An electronic system, in some embodiments, comprises: a power source; a load coupled to the power source; an analog-to-digital converter, coupled to the power source and the load, that samples a fluctuating voltage supplied by the power source and generates a digital representation of said fluctuating voltage; control logic, coupled to the analog-to-digital converter, that generates an amplitude correction signal based on said digital representation of the fluctuating voltage and on a target voltage; correction logic, coupled to the control logic, that uses the amplitude correction signal and an audio signal to generate a switch control signal; and an output driver, coupled to the correction logic, that controls coupling between the power source and the load based on the switch control signal.
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