MIPI C-PHY and D-PHY Interface with Shared Driver, Equalization, and Data Path Circuitry

    公开(公告)号:US20240314466A1

    公开(公告)日:2024-09-19

    申请号:US18182644

    申请日:2023-03-13

    CPC classification number: H04N25/766 H04N25/767 H04N25/7795 H04L7/0087

    Abstract: Imaging circuitry may include half-driver sub-circuits configured to support Mobile Industry Processor Interface (MIPI) D-PHY mode and C-PHY mode. Groups of two half-driver sub-circuits can be coupled together in the D-PHY mode, whereas groups of three half-driver sub-circuits can be coupled together in the C-PHY mode. Each half-driver sub-circuit can include one or more pull-up paths and one or more pull-down paths. Each half-driver sub-circuit can include multiple slices, a first portion of which can be operated to pull in a first direction and a second portion of which can be operated to pull in a second direction opposing the first direction to achieve the desired amount of equalization. The half-driver sub-circuits can be employed as the final driver stage of a shared data path architecture supporting both D-PHY and C-PHY modes. The shared data path can include serializers, pre-driver logic, and/or equalization enable blocks.

    COMMUNICATIONS CHANNEL WITH MULTI-LEVEL SIGNAL TRANSMISSION

    公开(公告)号:US20230011466A1

    公开(公告)日:2023-01-12

    申请号:US17455306

    申请日:2021-11-17

    Abstract: A system may include multiple electrical components. One electrical component such as an imaging sub-system may be communicatively coupled to another electrical component such as control circuitry for the system. The imaging-subsystem may include transmitter circuitry. The transmitter circuitry can include driver circuitry configured to provide the transmitter circuitry output using a multi-level signaling scheme. To generate the control signals for the driver circuitry, pre-driver combinational logic may precede the serializer circuitry and be coupled to the word data latch circuitry. In such a manner, the generated control signals for different portions of the driver circuitry can be better synchronized with one another, thereby helping improve data EYE margin in the multi-level signal scheme.

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