公开(公告)号：US20030141434A1

公开(公告)日：2003-07-31

申请号：US10200332

申请日：2002-07-23

申请人： SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER

发明人： Masatoshi Ishikawa ,  Idaku Ishii ,  Takashi Komuro ,  Shingo Kagami

IPC分类号： H01L027/00

CPC分类号： G01J1/4228 ,  G01J1/0204 ,  H04N5/335

摘要： A semiconductor integrated circuit device, having a plurality of processing elements accommodated on a single semiconductor chip, has a latch circuit and a selecting circuit. The latch circuit is provided at an output of each of the processing elements. The selecting circuit selects an input source from a group consisting of upper, lower, left, and right processing elements and a zero signal.

摘要翻译： 具有容纳在单个半导体芯片上的多个处理元件的半导体集成电路器件具有锁存电路和选择电路。 锁存电路设置在每个处理元件的输出处。 选择电路从由上，下，左，右处理元件组成的组和零信号中选择输入源。