公开(公告)号：US20240397699A1

公开(公告)日：2024-11-28

申请号：US18570810

申请日：2023-10-17

Applicant: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION

Inventor： Cheol Seong Hwang ,  Seo Young Jang ,  Han Chul Lee

IPC: H10B12/00

Abstract: The present disclosure discloses a capacitorless three-dimensional stacked DRAM device including a plurality of memory cell structures spaced apart from each other in horizontal and vertical directions, each of the plurality of memory cell structures including a horizontal read transistor structure and a horizontal write transistor structure, a plurality of write bit lines connected to the plurality of write transistor structures of the plurality of memory cell structures and extending in the horizontal direction, a plurality of read bit lines connected to the plurality of read transistor structures of the plurality of memory cell structures and extending in the horizontal direction, a plurality of write word lines connected to the plurality of write transistor structures and extending in the vertical direction, and a plurality of read word lines connected to the plurality of read transistor structures and extending in the vertical direction.

公开(公告)号：US20250098140A1

公开(公告)日：2025-03-20

申请号：US18577057

申请日：2023-10-23

Applicant: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION

Inventor： Cheol Seong Hwang ,  Sun Jin Lee ,  Seo Young Jang

IPC: H10B12/00

Abstract: The present disclosure discloses a capacitorless 3D DRAM device including a write bit line extending in a vertical direction, a write word line extending in a horizontal direction, a write transistor connected to the write bit line and the write word line, and defined to include a first channel material layer, a first gate insulating layer, and a portion of the write word line, a read bit line extending in the vertical direction, a read word line extending in the horizontal direction, and a read transistor connected to the read bit line and the read word line.