公开(公告)号：US20240143883A1

公开(公告)日：2024-05-02

申请号：US18203662

申请日：2023-05-31

Applicant: SHANGHAITECH UNIVERSITY

Inventor： Jianwen LUO ,  Yajun HA

IPC: G06F30/347 ,  G06F30/31

CPC classification number: G06F30/347 ,  G06F30/31

Abstract: A layout method for a scalable multi-die network-on-chip FPGA architecture is provided. An application of the aforementioned layout method for the scalable multi-die network-on-chip FPGA architecture is further provided. A scalable multi-die FPGA architecture based on network-on-chip and a corresponding hierarchical recursive layout algorithm are provided, aiming to directly map a register transfer level dataflow design generated by existing high-level synthesis onto the provided interconnection architecture. The layout method can exploit the potential for hierarchical topology and make more efficient use of dedicated interconnection resources, such as cross-die nets, network-on-chips, and high-speed transceivers.