公开(公告)号：US20240289914A1

公开(公告)日：2024-08-29

申请号：US18537836

申请日：2023-12-13

Applicant: SHANGHAITECH UNIVERSITY

Inventor： Lin LI ,  Yajun HA

IPC: G06T1/20 ,  G06F9/38

CPC classification number: G06T1/20 ,  G06F9/3851

Abstract: A graphics processing unit (GPU)-based logic rewriting acceleration method comprising parallelizing sub-procedures of And-Inverter Graph (AIG)-based logic rewriting. A recursive sub-procedure of the AIG-based logic rewriting is redesigned to be non-recursive, to provide sufficient parallelism for a GPU. In order to parallelize a replacement step on the GPU, the present disclosure uses a lock to ensure mutually exclusive access, which inevitably damages scalability of inter-node parallelism. In order to fully utilize the inter-node parallelism on a large scale, the present disclosure proposes a work scheduler that adds nodes with non-overlapping maximum fan-out-free cones (MFFCs) to a group, such that nodes in an MFFC can be deleted simultaneously without a conflict. In order to simultaneously create and delete a same node, the present disclosure also proposes a GPU-friendly graphical data structure to support these concurrent operations.