公开(公告)号：US20230305712A1

公开(公告)日：2023-09-28

申请号：US17942517

申请日：2022-09-12

Applicant: SK hynix Inc.

Inventor： Hye Mi KANG

IPC: G06F3/06

CPC classification number: G06F3/0617 ,  G06F3/0629 ,  G06F3/0679

Abstract: A memory controller includes: a program operation controller configured to control a memory device to store data and individual mapping information; a mapping information storage configured to store therein mapping information; a mapping information update controller configured to control the memory device to store the mapping information in a second memory block; perform an update operation of updating the mapping information, and delay, when sequentiality of a predetermined number or more of logical addresses is maintained with respect to the predetermined time, the update operation until the sequentiality is broken; and a Sudden Power Off Recovery (SPOR) controller configured to receive the individual mapping information, recover the mapping information for the data stored in the page during a delay section and provide the recovered mapping information to the mapping information storage.

公开(公告)号：US20210311879A1

公开(公告)日：2021-10-07

申请号：US16996243

申请日：2020-08-18

Applicant: SK hynix Inc.

Inventor： Hye Mi KANG

IPC: G06F12/10

Abstract: A memory system includes a memory device and a controller. The memory device includes at least one open memory block. The controller is configured to program data input along with write requests from an external device in the at least one open memory block, determine a storage mode regarding map data based on a type of the write requests, and perform a map update based on the map data. The controller is further configured to determine a timing for performing the map update is determined based on the storage mode and the type of write requests.

公开(公告)号：US20210026548A1

公开(公告)日：2021-01-28

申请号：US16698296

申请日：2019-11-27

Applicant: SK hynix Inc.

Inventor： Hye Mi KANG

IPC: G06F3/06 ,  G06F12/1009

Abstract: The present technology relates to an electronic device. A memory controller according to the present technology has improved map update performance. The memory controller controls a memory device that stores logical to physical map data indicating a mapping relationship between a logical address and a physical address of data. The memory controller includes a map data storage and a map data manager. The map data storage stores physical to logical (P2L) map data generated based on a logical address corresponding to a request received from a host. The map data manager performs a map update operation for the L2P map data by using some of an entire P2L map data stored in the map data storage, according to an amount of the P2L map data stored in the map data storage.

公开(公告)号：US20240211394A1

公开(公告)日：2024-06-27

申请号：US18327055

申请日：2023-06-01

Applicant: SK hynix Inc.

Inventor： Hye Mi KANG

IPC: G06F12/02

CPC classification number: G06F12/0292 ,  G06F12/023

Abstract: A memory system comprises a memory device configured to store data; and a memory controller configured to: classify and store access data for plural pieces of map information respectively, according to a cycle; assign different weights to plural pieces of access data, classified according to the cycle, to determine a priority of the plural pieces of map information; and transmit at least one map information to a host based on the priority.

公开(公告)号：US20220245064A1

公开(公告)日：2022-08-04

申请号：US17375472

申请日：2021-07-14

Applicant: SK hynix Inc.

Inventor： Hye Mi KANG

IPC: G06F12/0802

Abstract: The present technology relates to a memory controller according to an embodiment includes a map caching controller generating a slot allocation request to allocate a physical slot in which a first map segment is to be stored among a plurality of physical slots, a map buffer manager outputting the first map segment, first physical slot information, and tree slot information, in response to the slot allocation request, and a mapping manager receiving the first map segment, the first physical slot information, and the tree slot information, deleting a second map segment and second physical slot information stored in a tree slot among a plurality of tree slots of a map tree, and storing the first map segment and the first physical slot information in the tree slot. At least one of the second map segment and the second physical slot information stored in the tree slot is invalid.

公开(公告)号：US20220138099A1

公开(公告)日：2022-05-05

申请号：US17307868

申请日：2021-05-04

Applicant: SK hynix Inc.

Inventor： Hye Mi KANG

IPC: G06F12/02 ,  G06F12/0891

Abstract: An electronic device includes a memory system having improved performance. The memory system includes a memory device including memory blocks allocated to zones, a memory controller configured to send, to a host, a request for information on whether to perform a garbage collection operation on a target zone according to a trigger signal for performing a first internal operation, the target zone corresponding to a target memory block on which the first internal operation is to be performed, the target zone being included in the zones, and the host configured to provide the information on whether to perform the garbage collection operation to the memory controller based on information related to the zones, in response to the request. The memory controller determines whether to perform the first internal operation on the target memory block, based on the information on whether to perform the garbage collection operation.

公开(公告)号：US20220066696A1

公开(公告)日：2022-03-03

申请号：US17182008

申请日：2021-02-22

Applicant: SK hynix Inc.

Inventor： Hye Mi KANG

IPC: G06F3/06

Abstract: The present technology relates to an electronic device. A memory controller according to the present technology may include a host interface controller, a plurality of buffers, and a memory operation controller. The host interface controller may sequentially generate a plurality of commands based on a request received from a host. The plurality of buffers may store the plurality of commands according to command attributes. The memory operation controller may compare a sequence number of a target command stored in a target buffer among the plurality of buffers with a sequence number of a standby command stored in remaining buffers, and may determine a process of the target command and a process of the standby command based on a comparison. wherein a buffer satisfying a flush condition among the plurality of buffers is selected as the target buffer.

公开(公告)号：US20220004332A1

公开(公告)日：2022-01-06

申请号：US17148116

申请日：2021-01-13

Applicant: SK hynix Inc.

Inventor： Hye Mi KANG ,  Eu Joon BYUN

IPC: G06F3/06

Abstract: A memory controller for controlling a memory device which stores logical-to-physical (L2P) segments includes a map data storage and a map manager. The map data storage stores a plurality of physical-to-logical (P2L) segments including mapping information between a physical address of the memory device in which write data is to be stored and a logical address received from a host, in response to a write request received from the host. The map manager updates the L2P segments stored in the memory device, based on target P2L segments corresponding to a write command provided to the memory device, which have a higher priority than the other P2L segments among the plurality of P2L segments. Each of L2P segments includes mapping information between a logical address and a physical address of data stored in the memory device.

公开(公告)号：US20210109852A1

公开(公告)日：2021-04-15

申请号：US16895019

申请日：2020-06-08

Applicant: SK hynix Inc.

Inventor： Hye Mi KANG ,  Eu Joon BYUN

IPC: G06F12/02 ,  G06F12/06 ,  G06F12/0873 ,  G06F1/14 ,  G06F1/12

Abstract: Provided herein may be a controller and a data storage system having the controller. The controller may include a mapping time generator configured to generate a first mapping time at which a logical block address and a physical block address are mapped to each other, an internal memory configured to store first address mapping information including an address map, and the first mapping time, a host interface configured to transmit the first address mapping information to a host, and receive second address mapping information from the host, and a central processing unit configured to generate the address map, store the first address mapping information in the internal memory, compare a second mapping time included in the second address mapping information with the first mapping time, and select a read mode based on a result of the comparison.

公开(公告)号：US20230297248A1

公开(公告)日：2023-09-21

申请号：US17984484

申请日：2022-11-10

Applicant: SK hynix Inc.

Inventor： Hye Mi KANG

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0653 ,  G06F3/0679

Abstract: A memory controller includes a data detection circuit configured to detect, when power is supplied after a sudden power-off (SPO), a lost write sequence index “M” among the plural write sequence indexes, and detect first data corresponding to a write sequence index “M−1” and second data corresponding to a write sequence index “M+1”; a barrier decision circuit configured to determine, based on whether first barrier information of the first data and second barrier information of the second data are identical with each other, whether a barrier request for the first data has been received from a host; and a data recovery operation determination circuit configured to determine whether to perform a recovery operation on target data corresponding to the write sequence index “M+1” and thereafter based on whether the barrier request for the first data has been received.