公开(公告)号：US20210174184A1

公开(公告)日：2021-06-10

申请号：US17181595

申请日：2021-02-22

Applicant: SOUTHEAST UNIVERSITY

Inventor： Weiwei SHAN ,  Ziyu LI ,  Jun YANG ,  Longxing SHI

IPC: G06N3/063 ,  G06N3/04

Abstract: The present invention discloses an ultralow-power negative margin timing monitoring method of a neural network circuit, relates to an adaptive voltage regulation technology based on on-chip timing detection, and belongs to the technical field of low-power design of integrated circuit. The present invention provides an ultralow-power operating method of neural network circuit. By inserting a timing monitoring unit in specific position of critical paths and setting partial circuits to operate under “negative margin”, the system can further lower voltage, compress the timing slack, and obtain higher power gain.