公开(公告)号：US20230411504A1

公开(公告)日：2023-12-21

申请号：US18029990

申请日：2021-08-18

Applicant: SOUTHERN UNIVERSITY OF SCIENCE AND TECHNOLOGY

Inventor： Mengyuan HUA ,  Junting CHEN

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/10

CPC classification number: H01L29/7786 ,  H01L29/1066 ,  H01L29/2003

Abstract: A P-type gate HEMT device includes a substrate, a buffer layer, a channel layer, and a barrier layer sequentially arranged from bottom to top. A first P-type material layer is arranged on the barrier layer. A first source and a first drain are respectively arranged on two sides of the first P-type material layer. A first conductive layer is arranged on the first P-type material layer. A second P-type material layer is connected to the first P-type material layer. A second conductive layer is connected to the second P-type material layer. A third conductive layer is connected to the second P-type material layer. The first P-type material layer, the first source, the first drain, and the first conductive layer form a normally-off N-channel transistor. The second P-type material layer, the second conductive layer, and the third conductive layer form a normally-on P-channel transistor.