公开(公告)号：US20150249382A1

公开(公告)日：2015-09-03

申请号：US14426761

申请日：2013-08-15

Applicant: ST-ERICSSON SA

Inventor： Philippe Pignolo

IPC: H02M1/36 ,  H02M3/158

CPC classification number: H02M1/36 ,  H02M3/158

Abstract: A method of controlling a start-up sequence of a DC/DC Buck converter, the method being characterised by the steps of continuously comparing the Buck converter's output voltage with an internal reference voltage and continuously monitoring for a Buck converter start-up signal, wherein if the output voltage is greater than the reference voltage when a Buck converter start-up signal is detected, switching off the Buck converter and discharging an output capacitor of the Buck converter through a pull-down unit until the output voltage substantially equals the internal reference voltage and then restarting the Buck converter.

Abstract translation: 一种控制DC / DC降压转换器的启动顺序的方法，该方法的特征在于以下步骤：将降压转换器的输出电压与内部参考电压进行连续比较，并连续监测降压转换器启动信号，其中 如果当检测到降压转换器启动信号时输出电压大于参考电压，则关闭降压转换器并通过下拉单元对降压转换器的输出电容放电直到输出电压基本上等于内部参考 电压然后重新启动降压转换器。

公开(公告)号：US09531254B2

公开(公告)日：2016-12-27

申请号：US14426761

申请日：2013-08-15

Applicant: ST-Ericsson SA

Inventor： Philippe Pignolo

IPC: H02M1/36 ,  H02M3/158

CPC classification number: H02M1/36 ,  H02M3/158

Abstract: A method of controlling a start-up sequence of a DC/DC Buck converter includes continuously comparing the Buck converter's output voltage with an internal reference voltage and continuously monitoring for a Buck converter start-up signal. If the output voltage is greater than the reference voltage when a Buck converter start-up signal is detected, the Buck converter is switched off and an output capacitor of the Buck converter is discharged through a pull-down unit until the output voltage substantially equals the internal reference voltage and then restarting the Buck converter.

Abstract translation: 一种控制DC / DC降压转换器的启动顺序的方法包括连续地将Buck转换器的输出电压与内部参考电压进行比较，并连续监测降压转换器启动信号。 如果在检测到降压转换器启动信号时输出电压大于参考电压，则降压转换器关闭，降压转换器的输出电容通过下拉单元放电直到输出电压基本等于 内部参考电压，然后重新启动降压转换器。

公开(公告)号：US09490776B2

公开(公告)日：2016-11-08

申请号：US14438727

申请日：2013-11-15

Applicant: ST-Ericsson SA

Inventor： Philippe Pignolo

IPC: H03K3/017 ,  H02M3/156 ,  H03K3/012

CPC classification number: H03K3/017 ,  H02M3/156 ,  H02M2003/1566 ,  H03K3/012

Abstract: A pulse width modulation controller (PWM) is disclosed which has a MOSFET (15) responsive to the error voltage (Verror) signal from the PWM amplifier (17) to detect a transient condition without delay ΔTd. The MOSFET drain generates and applies a detection signal (S) to a delaying circuit (D). The delaying circuit (D) is responsive to the transient detection signal (S) to asynchronously output two latch signals (S1) and (S2) which on application to respective latch circuits (L1, L2) cause a change in conduction state of PMOS (8) and NMOS (9). This arrangement reduces voltage undershoot.

Abstract translation: 公开了一种脉冲宽度调制控制器（PWM），其具有响应于来自PWM放大器（17）的误差电压（Verror）信号的MOSFET（15），以无延迟ΔTd检测瞬态条件。 MOSFET漏极产生并向延迟电路（D）施加检测信号（S）。 延迟电路（D）响应于瞬态检测信号（S）以异步地输出两个锁存信号（S1）和（S2），其在应用于各个锁存电路（L1，L2）引起PMOS的导通状态的改变 8）和NMOS（9）。 这种布置降低了电压下冲。

公开(公告)号：US20150256159A1

公开(公告)日：2015-09-10

申请号：US14438727

申请日：2013-11-15

Applicant: ST-ERICSSON SA

Inventor： Philippe Pignolo

IPC: H03K3/017 ,  H03K3/012

CPC classification number: H03K3/017 ,  H02M3/156 ,  H02M2003/1566 ,  H03K3/012

Abstract: A pulse width modulation controller (PWM) is disclosed which has a MOSFET (15) responsive to the error voltage (Verror) signal from the PWM amplifier (17) to detect a transient condition without delay ΔTd. The MOSFET drain generates and applies a detection signal (S) to a delaying circuit (D). The delaying circuit (D) is responsive to the transient detection signal (S) to asynchronously output two latch signals (S1) and (S2) which on application to respective latch circuits (L1, L2) cause a change in conduction state of PMOS (8) and NMOS (9). This arrangement reduces voltage undershoot.

Abstract translation: 公开了一种脉冲宽度调制控制器（PWM），其具有响应于来自PWM放大器（17）的误差电压（Verror）信号的MOSFET（15），以无延迟地检测瞬态状态和Dgr; Td。 MOSFET漏极产生并向延迟电路（D）施加检测信号（S）。 延迟电路（D）响应于瞬态检测信号（S）异步地输出两个锁存信号（S1）和（S2），在锁存信号（S1，L2）施加到各个锁存电路（L1，L2）导致PMOS导通状态 8）和NMOS（9）。 这种布置降低了电压下冲。