公开(公告)号：US08797069B2

公开(公告)日：2014-08-05

申请号：US13910366

申请日：2013-06-05

Applicant: ST-Ericsson SA

Inventor： Leonardus Hesen ,  Paul Mateman ,  Johannes Petrus Antonius Frambach

IPC: H03K21/00

CPC classification number: H03K21/00 ,  H03K21/026 ,  H03K21/12

Abstract: High-speed RF differential, Quadrature, divide-by-2 clock divider designs are based on inverters and clocking circuits connected in a serial ring formation. In one embodiment, only NMOS transistors are used in the inverters, and only PMOS transistors are used in the clocking circuits. This structure uses only 12 transistors. The input can be coupled directly to a VCO output, and provides minimum loading, as each VCO output is connected to only two transistors. Another embodiment comprises clocked inverter stages connected in a serial ring configuration with inverters between stages. The RF clock (or VCO signal) is used at the outer side of the inverters for speed improvement. In both circuits, positive and negative clock inputs are connected alternately at each stage of the ring.

Abstract translation: 高速RF差分，正交，2分频时钟分频器设计基于以串联环形形式连接的逆变器和时钟电路。 在一个实施例中，在反相器中仅使用NMOS晶体管，并且在时钟电路中仅使用PMOS晶体管。 该结构仅使用12个晶体管。 由于每个VCO输出仅连接到两个晶体管，输入可以直接耦合到VCO输出，并提供最小的负载。 另一个实施例包括以串联环形连接的时钟反相级，在级之间具有反相器。 逆变器外侧使用RF时钟（或VCO信号）进行速度改进。 在两个电路中，正和负时钟输入在环的每个阶段交替连接。

公开(公告)号：US20130293272A1

公开(公告)日：2013-11-07

申请号：US13910366

申请日：2013-06-05

Applicant: ST-Ericsson SA

Inventor： Leonardus Hesen ,  Paul Mateman ,  Johannes Petrus Antonius Frambach

IPC: H03K21/00

CPC classification number: H03K21/00 ,  H03K21/026 ,  H03K21/12

Abstract: High-speed RF differential, Quadrature, divide-by-2 clock divider designs are based on inverters and clocking circuits connected in a serial ring formation. In one embodiment, only NMOS transistors are used in the inverters, and only PMOS transistors are used in the clocking circuits. This structure uses only 12 transistors. The input can be coupled directly to a VCO output, and provides minimum loading, as each VCO output is connected to only two transistors. Another embodiment comprises clocked inverter stages connected in a serial ring configuration with inverters between stages. The RF clock (or VCO signal) is used at the outer side of the inverters for speed improvement. In both circuits, positive and negative clock inputs are connected alternately at each stage of the ring.

Abstract translation: 高速RF差分，正交，2分频时钟分频器设计基于以串联环形形式连接的逆变器和时钟电路。 在一个实施例中，在反相器中仅使用NMOS晶体管，并且在时钟电路中仅使用PMOS晶体管。 该结构仅使用12个晶体管。 由于每个VCO输出仅连接到两个晶体管，输入可以直接耦合到VCO输出，并提供最小的负载。 另一个实施例包括以串联环形连接的时钟反相级，在级之间具有反相器。 逆变器外侧使用RF时钟（或VCO信号）进行速度改进。 在两个电路中，正和负时钟输入在环的每个阶段交替连接。