公开(公告)号：US20210111109A1

公开(公告)日：2021-04-15

申请号：US17131222

申请日：2020-12-22

Applicant: STMICROELECTRONICS, INC.

Inventor： Rennier RODRIGUEZ ,  Aiza Marie AGUDON ,  Maiden Grace MAMING

IPC: H01L23/495 ,  H01L23/64

Abstract: The present disclosure is directed to a flat no-lead semiconductor package with a surfaced mounted structure. An end portion of the surface mounted structure includes a recessed member so that the surface mounted structure is coupled to leads of the flat no-lead semiconductor package through, among others, the sidewalls of the recessed members.

公开(公告)号：US20230253213A1

公开(公告)日：2023-08-10

申请号：US18303471

申请日：2023-04-19

Applicant: STMicroelectronics, Inc.

Inventor： Rennier RODRIGUEZ ,  Maiden Grace MAMING ,  Jefferson Sismundo TALLEDO

IPC: H01L21/48 ,  H01L23/495 ,  H01L23/00

CPC classification number: H01L21/4825 ,  H01L23/49513 ,  H01L23/562 ,  H01L23/49548 ,  H01L24/29 ,  H01L23/49503 ,  H01L23/49541

Abstract: The present disclosure is directed to a lead frame including a die pad with cavities, and methods for attaching a semiconductor die to the lead frame. The cavities allow for additional adhesive to be formed on the die pad at the corners of the semiconductor die, and prevent the additional adhesive from overflowing on to active areas of the semiconductor die.

公开(公告)号：US20190267310A1

公开(公告)日：2019-08-29

申请号：US16264824

申请日：2019-02-01

Applicant: STMicroelectronics, Inc.

Inventor： Rennier RODRIGUEZ ,  Maiden Grace MAMING ,  Jefferson TALLEDO

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/48

Abstract: The present disclosure is directed to a lead frame including a die pad with cavities, and methods for attaching a semiconductor die to the lead frame. The cavities allow for additional adhesive to be formed on the die pad at the corners of the semiconductor die, and prevent the additional adhesive from overflowing on to active areas of the semiconductor die.

公开(公告)号：US20210265245A1

公开(公告)日：2021-08-26

申请号：US17317818

申请日：2021-05-11

Applicant: STMicroelectronics, Inc.

Inventor： Rennier RODRIGUEZ ,  Maiden Grace MAMING ,  Jefferson TALLEDO

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/00

Abstract: The present disclosure is directed to a lead frame including a die pad with cavities, and methods for attaching a semiconductor die to the lead frame. The cavities allow for additional adhesive to be formed on the die pad at the corners of the semiconductor die, and prevent the additional adhesive from overflowing on to active areas of the semiconductor die.

公开(公告)号：US20210183750A1

公开(公告)日：2021-06-17

申请号：US17185742

申请日：2021-02-25

Applicant: STMicroelectronics, Inc.

Inventor： Rennier RODRIGUEZ ,  Aiza Marie AGUDON ,  Jefferson TALLEDO ,  Moonlord MANALO ,  Ela Mia CADAG ,  Rammil SEGUIDO

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: The present disclosure is directed to a leadframe having a recess in a body of the leadframe to collect glue overflowing from the manufacturing process of coupling a semiconductor die to the leadframe. The recess extends beneath an edge of the semiconductor die so that any tendency of the glue to adhere to the semiconductor die is counteracted by a tendency of the glue to adhere to a wall of the recess and at least partially fill the volume of the recess. In addition, the recess for collecting adhesive may also form a mold lock on an edge of the leadframe, the mold lock providing a more durable connection between the leadframe and an encapsulant during physical and temperature stresses.

公开(公告)号：US20220005782A1

公开(公告)日：2022-01-06

申请号：US17479988

申请日：2021-09-20

Applicant: STMicroelectronics, Inc.

Inventor： Rennier RODRIGUEZ ,  Rammil SEGUIDO ,  Raymond Albert NARVADEZ ,  Michael TABIERA

IPC: H01L23/00 ,  H01L23/495

Abstract: The present disclosure is directed to a semiconductor die with multiple contact pads electrically coupled to a single lead via a single wire, and methods for fabricating the same. In one or more embodiments, multiple contact pads are electrically coupled to each other by a plurality of conductive layers stacked on top of each other. The uppermost conductive layer is then electrically coupled to a single lead via a single wire.

公开(公告)号：US20210391226A1

公开(公告)日：2021-12-16

申请号：US17346766

申请日：2021-06-14

Applicant: STMICROELECTRONICS, INC.

Inventor： Rennier RODRIGUEZ ,  John Alexander SORIANO ,  Aaron CADAG

IPC: H01L23/043 ,  H01L21/48 ,  H01L21/52 ,  H01L23/495

Abstract: One or more embodiments are directed to semiconductor device packages having a cap with integrated metal interconnects or conductive leads. One embodiment is directed to a semiconductor device package that includes a cap having a cover extending along a first direction and sidewalls extending from the cover along a second direction that is transverse to the first direction. A plurality of electrical leads are disposed on inner surfaces of the sidewalls and extend over lower surfaces of the sidewalls. A semiconductor die is attached to an inner surface of the cover of the cap, and the semiconductor die is electrically coupled to the plurality of electrical leads.

公开(公告)号：US20210151368A1

公开(公告)日：2021-05-20

申请号：US17139669

申请日：2020-12-31

Applicant: STMICROELECTRONICS, INC.

Inventor： Rennier RODRIGUEZ ,  Aiza Marie AGUDON ,  Maiden Grace MAMING

IPC: H01L23/495 ,  H01L23/64

Abstract: The present disclosure is directed to a flat no-lead semiconductor package with a surfaced mounted structure. An end portion of the surface mounted structure includes a recessed member so that the surface mounted structure is coupled to leads of the flat no-lead semiconductor package through, among others, the sidewalls of the recessed members.

公开(公告)号：US20220139845A1

公开(公告)日：2022-05-05

申请号：US17509758

申请日：2021-10-25

Applicant: STMICROELECTRONICS, INC.

Inventor： Endalicio MANALO ,  Rennier RODRIGUEZ

IPC: H01L23/552 ,  H01L23/495 ,  H01L23/29 ,  H01L23/31

Abstract: The present disclosure is directed to a semiconductor package that include a non-conductive encapsulation layer encapsulation an integrated circuit chip, and a conductive encapsulation layer over the non-conductive encapsulation layer. A lead is exposed from the non-conductive encapsulation layer and contacts the conductive encapsulation layer. The conductive encapsulation layer and the lead provide EMI shielding for the integrated circuit chip.

公开(公告)号：US20190148271A1

公开(公告)日：2019-05-16

申请号：US16249612

申请日：2019-01-16

Applicant: STMicroelectronics, Inc.

Inventor： Rennier RODRIGUEZ ,  Raymond Albert NARVADEZ ,  Ernesto ANTILANO, JR.

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/31 ,  H01L21/56

Abstract: The present disclosure is directed to a leadframe package having leads with protrusions on an underside of the leadframe. The protrusions come in various shapes and sizes. The protrusions extend from a body of encapsulant around the leadframe to couple to surface contacts on a substrate. The protrusions have a recess that is filled with encapsulant. Additionally, the protrusions may be part of the lead or may be a conductive layer on the lead. In some embodiments a die pad of the leadframe supporting a semiconductor die also has a protrusion on the underside of the leadframe. The protrusion on the die pad has a recess that houses an adhesive and at least part of the semiconductor die. The die pad with a protrusion may include anchor locks at the ends of the die pad to couple to the encapsulant.